Along with developments of the semiconductor packaging technology, there have been produced many different packaging types of semiconductor devices. In the semiconductor device, a semiconductor chip is mounted on a package substrate or lead frame, and then electrically connected to the package substrate or lead frame; subsequently, an encapsulant is fabricated to encapsulate the chip and form a package. Ball Grid Array (BGA) package involves an advanced type of the semiconductor packaging technology, which is characterized by the use of a package substrate whose front side is mounted with a semiconductor chip and whose back side is implanted with a grid array of solder balls using a self-alignment technique. This allows more input/output (I/O) connections to be accommodated on the same unit area of a chip carrier (i.e. package substrate), so as to meet the requirement for a highly integrated semiconductor chip, such that the entire package can be electrically connected to an external device by means of the solder balls.
Referring to the conventional BGA semiconductor package, the semiconductor chip is mounted on the front side of the substrate and electrically connected to the substrate by a wire-bonding or flip-chip technique; then, the solder balls are implanted on the back side of the substrate to provide the I/O connections. Although the requirement for a large number of I/O connections is met, during high-frequency usage or high-speed operation, the quality of electrical performance cannot be maintained due to the excessively long electrically conductive path in such BGA package. Furthermore, the conventional packaging technology requires multiple connection interfaces, therefore increasing the fabrication cost thereof.
Accordingly, in order to effectively improve the electrical performance for the requirement of the next generation of products, there has been proposed to embed chips in a substrate and establish direct electrical connection between the chips and substrate so as to shorten the electrically conductive path and reduce signal losses and signal failures as well as improve the performance at high-speed operate.
Referring to FIG. 1, in order to embed a chip in an opening of a circuit board, firstly, at least one semiconductor chip 11 is mounted on a carrier film 10 in an upside-down manner that an active surface 110 of the chip 11 is attached to the carrier film 10. Subsequently, the carrier film 10 mounted with the chip 11 is attached to a support plate 12 having a predetermined opening 120, allowing the chip 11 to be received in the opening 120 of the support plate 12. The carrier film 10 is used to maintain flatness and height consistency of electrode pads 111 formed on the active surface 110 of the chip 11, such that electrical connection between the active surface 110 of the chip 11 and the support plate 12 can be effectively established after removing the carrier film 10.
In the above method, although the height consistency of the electrode pad 111 on the active surface 110 of the chip 11 is well maintained, when the chip 11 mounted on the carrier film 10 is embedded in the opening 120 of the support plate 12, an alignment error between the chip 11 and the opening 120 of the support plate 12 may occur due to expansion/contraction of the carrier film 10 during a temperature cycle of semiconductor device fabrication processes, thereby degrading the reliability of subsequent fabrication processes. Furthermore, the use of the carrier film 10 not only increases the fabrication cost but also may generate and release organic substances during high-temperature fabrication processes to contaminate the chip 11 mounted thereon.
FIG. 2 shows another method of embedding a semiconductor chip 21 in an opening 220 of a support plate 22. The semiconductor chip 21 is placed into the opening 220 of the support plate 22 one by one. Then, a resin 20 having a copper foil 200 is pressed onto the support plate 22 embedded with the chip 21 to allow the resin 20 to encapsulate the chip 21; or alternatively, the resin 20 can be directly filled in the opening 220 of the support plate 22 to fix the chip 21.
However, by the above method, the fabricated structure may have poor flatness due to the direct application of the resin 20 and makes it hard to be used in an advanced integrated circuit product. Moreover, although the resin 20 having the copper foil 200 may provide height consistency for an active surface 210 of the chip 21, it is not suitable for fabrication of fine circuits since an etching technique is employed to perform circuit fabrication on the copper foil 200. Furthermore, the number of circuit layers needs to be increased to meet the requirements of advanced products, such that the fabrication cost is increased while the size miniaturization of the product is not facilitated as a consequence.